Resource-constrained FPGA implementation of YOLOv2

Abstract Progress is being made to deploy convolutional neural networks (CNNs) into the Internet of Things (IoT) edge devices for handling image analysis tasks locally. These require low-latency and low-power computation on low-resource IoT devices. However, CNN-based algorithms, e.g. YOLOv2, typically contain millions parameters. With increase in CNN’s depth, filters are increased by a power two. A large number operations could lead frequent off-chip memory access that affects operation speed consumption device. Therefore, it challenge map deep CNN platform. To address this challenge, we present resource-constrained Field-Programmable Gate Array implementation YOLOv2 with optimized data transfer computing efficiency. Firstly, scalable cross-layer dataflow strategy proposed which allows on-chip between different types layers, offers flexible when intermediate results unaffordable on-chip. Next, filter-level data-reuse together parallel multiply-accumulate processing elements array developed. Finally, multi-level sliding buffers developed optimize loop reuse input feature maps weights. Experiment show our has achieved 4.8 W executing an 8-bit containing 50.6 MB weights, using 8.3 Mbits memory. The throughput efficiency 100.33 GOP/s 20.90 GOP/s/W, respectively.